`timescale 1ns/1ps
`default_nettype none

module cxy_deal_frame_start(
    input  wire         I_sclk,
    input  wire         I_rst_n,

    input  wire         I_frame_start,
    output reg          O_fake_frame_start
    );
//***********************************************************
// 输入帧频<31Hz时，就在两个真实帧信号之间插入一个虚拟帧信号
localparam  CNT_FOR_FPS_31  = 1_000_000_000/(8*31);
localparam  CNT_FOR_FPS_24  = 1_000_000_000/(8*24);

reg     [23:0]  cnt;
reg     [23:0]  cnt_tmp;

//***********************************************************
//cnt[23:0]
always@(posedge I_sclk or negedge I_rst_n)
    if(!I_rst_n)
        cnt <= 1'b1;
    else if(I_frame_start)
        cnt <= 1'b1;
    else if(&cnt==0)
        cnt <= cnt + 1'b1;
        
//cnt_tmp[23:0]
always@(posedge I_sclk or negedge I_rst_n)
    if(!I_rst_n)
        cnt_tmp <= 'b0;
    else if(I_frame_start)
        cnt_tmp <= cnt;

//O_fake_frame_start
always@(posedge I_sclk or negedge I_rst_n)
    if(!I_rst_n)
        O_fake_frame_start <= 'b0;
    else if(cnt_tmp>CNT_FOR_FPS_31 && cnt_tmp<CNT_FOR_FPS_24 && cnt==cnt_tmp>>1)
        O_fake_frame_start <= 1'b1;
    else
        O_fake_frame_start <= 'b0;
//***********************************************************
endmodule

`default_nettype wire

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